This invention relates in general to a superjunction lateral double diffused metal oxide semiconductor field effect transistor (SJ-LDMOST) device fabricated on an insulator substrate. More specifically, the invention provides a device having improved on-state, off-state, and switching characteristics of lateral power devices for power integrated circuits applications.
The performance of power integrated circuits (PICs) relies heavily on the on-state and off-state characteristics of a family of lateral power metal oxide semiconductor field effect transistors (MOSFETs), termed lateral double diffused MOSFETs (LDMOSTs), that utilize the reduced surface field technique (RESURF) to achieve high breakdown voltage while maintaining low on-resistance. For a detailed description of RESURF lateral device technology refer to J. A. Appels and H. M. J. Vaes, xe2x80x9cHigh Voltage Thin Layer Devices (RESURF Devices)xe2x80x9d, IEEE International Electron Device Meeting (IEDM), Dig. Tech Papers, pp. 238-241, 1979; incorporated herein by reference. The cross-section of a RESURF LDMOST device 10 implemented in a bulk pxe2x88x92 type substrate 12 is shown in FIG. 1. The device 10 is typically fabricated on a thin epitaxial layer 14 to enhance the vertical depletion of the drift region 16. The device 10 further includes a source electrode 18, a drain electrode 20, a gate electrode 22, a polysilicon gate 24, a gate oxide layer 26, a field oxide layer 28, an n+ type source contact region 30, an n+ type drain contact region 32, and a p+ layer 34. Electrical isolation between adjacent devices is achieved by junction isolation (JI) where a reverse bias is applied to the p+ layer 34 at the source electrode 18.
In RESURF LDMOST devices, the specific on-resistance increases with the breakdown voltage due to the increase of the low doped drift region length LD. Optimum breakdown voltage is achieved provided that the product of the doping concentration ND and the thickness of the epitaxial layer, tepi, is in the order of 1 to 2xc3x971012 cmxe2x88x922 (known as the RESURF condition) which puts a limit on the upper bound of the doping concentration in the drift region and hence the minimum achievable specific on-resistance. Nevertheless breakdown voltages up to 1200V have been achieved using the RESURF technique and modifications of the technique such as a double RESURF device 36 structure, which includes a pxe2x88x92 region 38 in the surface of the nxe2x88x92 drift region 16, as shown in FIG. 2. For a detailed description of double RESURF technology, see J. S. Ajit, D. Kinzer and M. Ranjan,xe2x80x9d 1200V High-Side Lateral MOSFET in Junction-Isolated Power IC Technology Using Two Field Reduction Layersxe2x80x9d, Proceedings of the 5th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Proceedings, pp. 230-235, 1993; incorporated herein by reference.
The RESURF LDMOST may be fabricated on a silicon-on-insulator (SOI) substrate 40 as shown in FIG. 3. The technology is known as dielectrically isolated (DI) silicon technology. The dielectric isolation is achieved by inserting a buried oxide (BOX) layer 42 between the substrate 44 and the epitaxial layer 46, while lateral isolation 48 is carried out by either local oxidation of thin silicon films (LOCOS) or by trench etching and refilling the trench with a dielectric. Power devices and low voltage components in a PIC may be implemented in silicon islands that are completely surrounded by a dielectric allowing higher packing density. Other advantages provided by DI silicon technology include reduced leakage currents and low parasitic capacitances.
For RESURF LDMOST in SOI the vertical depletion in the drift region 16 is due to a field effect action through the intermediate BOX layer 42. The BV in this case is dependent on the charge in the top silicon epitaxial layer 46 as specified by the RESURF condition, the silicon layer thickness under the n+ diffusion, and the BOX thickness. Devices with uniform lateral electric field distribution are realized by using a laterally linear doping profile in the drift region resulting in BV of 860V for a silicon film thickness of 0.2 xcexcm and a BOX thickness of 4.4 xcexcm. For a detailed description of this type of device see S. Merchant, E. Arnold, H. Baumgart, R. Egloff, T. Letavic, S. Mukherjee, and H. Pein, xe2x80x9cDependence of Breakdown Voltage on Drift Length and Buried Oxide Thickness in SOI RESURF LDMOS Transistorxe2x80x9d, Proceedings of the 5th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Proceedings, pp. 124-128, 1993; incorporated herein by reference. Higher BV in DI technology requires thicker BOX layers, however, overly thick BOX layers may cause wafer warpage and bending, in addition, the effects of self-heating become more pronounced as the BOX thickness increases due to poor thermal conductivity of the oxide.
In high voltage LDMOSTs, the drift region resistance dominates the total on-resistance of the device. For breakdown voltages over 1200V the specific on-resistance of the LDMOST is impractically large. Therefore for further development of high voltage LDMOSTs, the emphasis has been to reduce the drift region resistance.
The superjunction concept may be applied to Vertical DMOSTs to achieve reduced on-resistance in devices having a high breakdown voltage. Superjunction vertical double diffused MOSFET (SJ-VDMOST) provide reduced resistivity of the drift region in vertical power devices.
The first discrete commercial SJ-VDMOST device 50, illustrated in FIG. 4, was introduced by Deboy et al. and labeled CoolMOS(trademark), which is the trademark of SIEMENS AG, of Munich, Germany. The device 50 includes a source electrode 18, a drain electrode 20, a gate electrode 22, channel regions 52, and alternatively stacked heavily doped n pillars 54 and p pillars 56 called SJ pillars 58. For a detailed description of the CoolMOS(trademark) device, see i) G. Deboy, M. Marz, J. P. Stengel, H. Strack, J. Tihanyi and H. Weber, xe2x80x9cA New Generation of High Voltage MOSFETs Breaks the Limits Line of Siliconxe2x80x9d, Proceedings of International Electron Devices Meeting (IEDM), pp. 683-685, 1998; and ii) L. Lorenz, G. Deboy, A. Knapp and M. Marz, xe2x80x9cCOOLMOS(trademark)xe2x80x94A New Milestone in High Voltage Power MOSxe2x80x9d, Proceedings of the 11th International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp. 3-10, 1999; incorporated herein by reference. The CoolMOS(trademark) structure achieves a factor of 5 reduction in the on resistance with respect to a state of the art conventional 600V VDMOST. At the same time the device demonstrates superior switching characteristics.
The CoolMOS(trademark) structure is based on the SJ concept. For a detailed description of the theoretical background work of the SJ concept applied to semiconductor devices, see i) U.S. Pat. No. 4,754,310; ii) U.S. Pat. No. 5,216,275; iii) U.S. Pat. No. 5,438,215; and iv) X. B. Chen, P. A. Mawby, K. Board, C. A. T. Salama, xe2x80x9cTheory of a Novel Voltage Sustaining Layer for Power Devicesxe2x80x9d, Microelectronics Journal, vol. 29, pp. 1005-1011, 1998; incorporated herein by reference. The SJ concept may be explained with the aid of FIG. 5. The SJ concept is based on achieving charge compensation in the SJ drift region 60 which may be realized by replacing the low doped drift region in a VDMOST with alternatively stacked, heavily doped n pillars 54 and p pillars 56; SJ pillars 58. When a reverse bias is applied to the SJ pillars 58 (forward blocking mode), an electric field is established which depletes the SJ pillars 58 of their charge carriers moving them in opposite directions towards their respective ohmic contacts 62 and 64 as shown in FIG. 5(a). The depletion region edges spread out of the SJs 66 (the junctions between the n pillars 54 and p pillars 56) towards depletion edges extending from neighboring SJs 66.
During this initial stage of the blocking mode the electric field increases fairly rapidly. Once depletion regions from adjacent SJs 66 merge the SJ drift region 60 becomes completely depleted of charge carriers and the bound (equal but opposite) charge in the n pillars and p pillars cancel each other out causing the net charge across the SJ drift region 60 to be effectively zero. The electric field distribution is spread uniformly over the SJ drift region 60 as shown in FIG. 5(b) and the electric field distribution in the SJ drift region 60 rises slowly with the increase of the reverse bias until the critical electric filed is reached at the breakdown point, and the breakdown mechanism in a SJ drift region 60 is governed by the impact ionization process. The incremental rise of the electric field in the SJ drift region 60 as a result of the increase in the reverse bias is inversely proportional to the SJ drift region 60 length LD.
The SJ structure results in: i) a flat electric field distribution in the SJ drift region 60 which yields the highest possible breakdown voltage (for a given drift region length) which is independent of the doping concentration of the SJ drift region 60 and ii) a significant improvement of the specific on-resistance achieved by using high doping concentrations in the n pillars 54. The doping of the n pillars 54 may be increased by as high as one to two order of magnitudes as compared to conventional structures thus compensating for the fact that half of the conducting area in the SJ drift region 60 is lost to the idle p pillars 56.
The main challenge in implementing SJ-VDMOST is the requirement for deep vertical SJ pillars 58, for example in 600V devices a SJ drift region 60 depth of about 35 xcexcm is required, this significantly increases the cost and time of manufacturing since it is estimated that at least 5 to 6 successive epitaxial processes (each followed by an ion-implantation process) are needed to achieve such deep SJ pillars 58.
Another method to fabricate a 250V SJ-VDMOST utilizes tilted ion implantation at a low-incident angle along the side walls of a deep trench (with aspect ratio=20 xcexcm/1.2 xcexcm). For a detailed description of a tilted ion implantation technique, see T. Nitta, T. Minato, M. Yano, A. Uensis, M. Harada, and S. Hine,xe2x80x9d Experimental Results and Simulation Analysis of 250V Super Trench Power MOSFET (STM)xe2x80x9d, Proceedings of the 12th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Proceedings, pp. 77-80, 1999; incorporated herein by reference. The n pillars 54 are formed by phosphorus ion implantation into one trench sidewall and the p pillars 56 are formed by boron ion implantation to the opposite sidewall as depicted in FIG. 6. The depth of the trench is limited by the minimum possible tilt angle that may be used to dope the bottom of the trench, therefore limited BV is achieved using this method. Another problem with this structure is the amount of the reflected ions due to the low incident angle is not negligible, these reflected ions are re-implanted to the opposite sidewall of the trench near the bottom causing an unintentional charge compensation and an uneven distribution of the pillars along the trench. This makes charge balance in the n and p stripes very difficult. Moreover the trench is subsequently refilled with oxide after the ion implantation process which means that the active area of the device is not fully utilized.
As in discrete SJ-VDMOST, the SJ concept may be applied to lateral power devices used in PICs where the chip area and power losses are of primary importance. For a description of lateral SJ devices, see T. Fujihira, xe2x80x9cTheory of Semiconductor Superjunction Devicesxe2x80x9d, Japan Journal of Applied Physics, Vol. 34, pp. 6254-6262, 1997; incorporated herein by reference. In lateral devices the drift region extends laterally as opposed to vertically as in the case of VDMOSTs, thus the requirement to fabricate deep pillars necessary for high voltage applications is eliminated.
Applying the SJ concept to lateral power devices faces several difficulties. In order to achieve high performance SJ-LDMOST devices several conditions must be met. The doping profiles in the n and p pillars must be high and tightly matched. Simulation results indicate that the BV is very sensitive to charge imbalance in the pillars as shown in FIG. 7, the sensitivity becoming more pronounced with the increase of doping levels in the pillars, indicating the existence of a trade off between the specific on-resistance and breakdown voltage sensitivity to charge imbalance. While in SJ-VDMOST this problem may be dealt with by developing a tightly controlled fabrication process. In lateral devices, in addition to the requirement of tightly matched profiles in the pillars, the design of SJ devices must account for the charge imbalance caused by the substrate-assisted-depletion which is an undesirable interaction between the SJ drift region and the finite resistivity substrate on which the device is built. For a detailed description of the substrate assisted depletion problems, see S. G. Nassif-Khalil, xe2x80x9cSuperjunction Lateral Devices for Power Integrated Circuitsxe2x80x9d, Ph.D Thesis Proposal, University of Toronto, 2000; incorporated herein by reference.
PICs are mainly implemented in silicon technology that uses either bulk or SOI substrates, in both cases the fact that the SJ drift region is terminated at the bottom by a silicon substrate results in a significant reduction of the breakdown voltage due to the existence of a vertical electric field component which gives a rise to a surplus of one type of charge in the pillars when a reverse bias is applied to the structure. This surplus increases monotonically towards the drain contact region and upsets the delicate charge balance between the n and p pillars.
The mechanisms by which the problematic surplus of charge is generated in the case of a bulk substrate and the case of an SOI substrate are different. In the implementation of an SJ-LDMOST device 68 on bulk substrates 70, shown in FIG. 8, pn junctions 72 are formed between the n pillars 54 and pxe2x88x92 type substrate 70, the pn junctions 72 in this case are horizontal while the SJs 66 are vertical. The horizontal junctions assist in depleting the n pillars 54 from the bottom, the extent of the depletion is not uniform and depends on the lateral position because there is a voltage gradient across the drift region. In other words, the region closer to the drain contact region 74 will be depleted more than regions away from the drain contact region 74, such as the regions which are in the immediate vicinity of the source electrode 18 and the gate electrode 22, as demonstrated in FIG. 9, which shows an equipotential contour plot of an SJ-LDMOST device 68.
In a similar fashion lateral SJ structures fabricated on an SOI substrate suffer from charge imbalance along the drift region, however, the induced charges are due to a field effect action generated by the capacitive structure consisting of the Silicon-BOX-Silicon sandwich with the top silicon epitaxial layer 46 acting as the top capacitance plate, the buried oxide layer 42 as the capacitance dielectric and the lower silicon substrate layer 44 as the capacitance bottom plate as indicated in FIG. 10, wherein the downwards arow depicts the direction of the problematic field effect action. For a detailed description of lateral structures fabricated on an SOI substrate, see Y. S. Huang and B. J. Baliga, xe2x80x9cExtension of RESURF Principle to Dielectrically Isolated Power Devicesxe2x80x9d, International Symposium on Power Semiconductor Devices and ICs (ISPSD). Proceedings, pp. 27-30, 1991; incorporated herein by reference. The amount of charge induced at the capacitance plates depends on the voltage across the capacitance and therefore varies across the SJ drift region 60 resulting in a charge surplus in one of the SJ pillars 54 or 56. This charge surplus increases monotonically towards the drain contact region 74.
It would therefore be desirable to eliminate the substrate-assisted-depletion effect in a SJ-LDMOST. A substrate must be provided which provides the necessary dielectric isolation for both low voltage and high voltage devices in a PIC, acts as mechanical support, and provides an effective thermal conductive path to minimize self-heating effects. It would therefore be desirable to implement a device structure which proposes a practical and a simple solution to these problems allowing the implementation of the SJ concept in lateral semiconductor devices.
The present invention provides a SJ-LDMOST device which significantly improves the on-state, off-state, and switching characteristics of lateral power devices for power integrated circuits applications. The device is fabricated on an insulator substrate. The device structure effectively solves the main problem encountered when applying the superjunction concept to lateral power devices, that is, the charge imbalance between the n and p SJ pillars which develops under reverse bias due to substrate-assisted-depletion which in turn results in a substantial reduction of the breakdown voltage BV in SJ lateral devices implemented in a finite resistivity substrate e.g. bulk or SOI. The device structure achieves charge compensation in the drift region by terminating the bottom of the SJ structure by a dielectric hence eliminating the undesirable vertical electric field component and preventing any substrate-assisted-depletion. The device structural arrangement thereby achieve a uniform distribution of the electric field thus maximizing the BV for a given drift region length. Due to the uniform electrical field distribution over the entire drift region, the BV increases rnonotonically with increasing drift region length LD and does not exhibit any saturation with the increase of LD as is the case in lateral SOI devices which are inhibited by the BOX thickness. Due to the relative ease by which the narrow SJ pillar deplete, the effective doping concentration in the drift region may be increased by a factor of 5 resulting in a significant improvement of the specific on-resistance over conventional lateral power devices.
In a preferred embodiment, the apparatus includes a lateral semiconductor device composed of an insulating substrate, a semiconductive layer formed on the insulating substrate, and a lateral power integrated circuit device formed in the semiconductive layer, having a superjunction drift region formed with a plurality of alternating heavily doped n pillars and p pillars.
Other advantages and features of the invention will become apparent from the following detailed description of the preferred embodiments and the accompanying drawings.